1. Field
Aspects of the present innovations are directed, generally, to providing low standby power consumption, and, more specifically, to providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
2. Description of Related Information
A known memory circuit 290 is set forth in a block schematic diagram shown in FIG. 1. Further, a representative operational timing diagram is illustrated in FIG. 2, showing how the control-i/o buffer enable circuit 231 operates and how the standby power is being consumed, respectively. Referring to FIG. 1, a memory circuit 290 may comprises a control-i/o buffer enable circuit 231, a control-peripheral 210A, an i/o-peripheral 210B, an internal-peripheral 230, and an array of memory cells 260. The internal-peripheral 230 may include circuitry such as an internal VDC 250, a DLL GEN 221, an active command 233, and a MRS command 232, among other components. The signal PWRUP1 is a first power up signal going on upon detection of ramp-up external power supply and configured to initialize control-peripheral 210A and internal VDC 250, while signal PWRUP2 is a second power up signal going on upon detection of ramp up of internal power supply and configured to initialize control-i/o buffer enable circuit 231, control-io-peripheral (210A and 210B), and internal-peripheral 230. Further, the signal BSR_RST may be configured for enabling BSCAN function, and other aspects (e.g. ports, and so forth) may be configured to generate various other internal signals.
In various circumstances in the circuits of FIG. 1, however, the signal IBON is held on the high level-state even though the power up initialization procedures are finished, while at the same time signal DBON is held on the low level-state (enabled only active in write command with the high level-state). Accordingly, such memory circuits will consume unnecessary standby power at group 2, group 4, group 5, group 6, and so forth, as viewed by way of illustration in connection with Table 1 below.
As set forth below, one or more aspects of the present inventions may overcome these or other drawbacks and/or otherwise impart innovative features.